Processing data, such as graphics and machine learning data, utilize computational resources such as multipliers and partial product adders. Data compression techniques are utilized in partial product adders to perform column addition operations in parallel, while keeping the sums separate from the carries. The product is realized by combining the final sum and carry using, as an example, normal addition.
Data compressors implement partial product reduction stages because they help reduce the partial products and they also reduce the critical path, which is desirable to maintain circuit performance. In a multiplier, partial product reduction trees may be implemented using XOR, half-adder, and full-adder gates, and may be the largest power consuming components. Moreover, the speed of data processing techniques may be adversely impacted by the rate at which partial product reduction occurs.